rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-batch16
Text Generation
•
8B
•
Updated
•
8
•
1
AI & ML interests
None defined yet.
models
159
rtl-llm/qwen2.5coder-7b-origen-vhdl-vhdl-verilog-chisel-gs16
Text Generation
•
8B
•
Updated
•
5
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-chisel-batch8
Text Generation
•
8B
•
Updated
•
3
rtl-llm/qwen2.5coder-7b-origen-vhdl-vhdl-verilog-gs16
Text Generation
•
8B
•
Updated
•
5
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-chisel
Text Generation
•
8B
•
Updated
•
5
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs32
Text Generation
•
8B
•
Updated
•
4
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-gs16
Text Generation
•
8B
•
Updated
•
3
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-len768
Text Generation
•
8B
•
Updated
•
5
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-fixed4o
Updated
rtl-llm/qwen2.5coder-7b-origen-vhdl-vhdl-chisel-gs16
Text Generation
•
8B
•
Updated
•
5
datasets
6
rtl-llm/vhdl_chisel_interleaved_fine
Updated
•
1
rtl-llm/chisel-verilog-pairs
Viewer
•
Updated
•
35.5k
•
36
•
2
rtl-llm/vhdl_github_deduplicated
Viewer
•
Updated
•
8.97k
•
4
rtl-llm/github_vhdl_verilog
Viewer
•
Updated
•
16.1k
•
7
rtl-llm/vhdl_github
Viewer
•
Updated
•
101k
•
38
•
1
rtl-llm/PyMTL_Verilog_pairs
Viewer
•
Updated
•
18.6k
•
16