code
stringlengths 35
6.69k
| score
float64 6.5
11.5
|
|---|---|
module mux #(
parameter WIDTH = 32
) (
input addr,
input [WIDTH-1:0] In0,
input [WIDTH-1:0] In1,
output reg [WIDTH-1:0] Out_dat
);
always @* begin
if (addr) Out_dat = In1;
else Out_dat = In0;
end
endmodule
| 8.575874
|
module control(rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel,
opcode, zero, clk, rst);
output rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel;
input [2:0] opcode;
input zero, clk, rst;
reg rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel;
reg [2:0] state; // state variable, necessary in explicit machines
`define HLT 3'b000
`define SKZ 3'b001
`define ADD 3'b010
`define AND 3'b011
`define XOR 3'b100
`define LDA 3'b101
`define STO 3'b110
`define JMP 3'b111
`define outputs {rd,wr,ld_ir,ld_acc,ld_pc,inc_pc,halt,data_e, sel}
`define LOG ((opcode == `ADD) || (opcode == `AND) || (opcode == `XOR) || (opcode == `LDA))
always @(posedge clk or negedge rst)
if (!rst)
{`outputs, state} <= 0;
else
begin
case (state)
3'b000 : `outputs <= 9'b000000001; // instruction fetch setup
3'b001 : `outputs <= 9'b100000001; // instruction fetch
3'b010 : `outputs <= 9'b101000001; // instruction load
3'b011 : `outputs <= 9'b101000001; // idle
3'b100 : if (opcode == `HLT) `outputs = 9'b000001100;
else `outputs <= 9'b000001000; // data fetch setup
// set mem_rd if opcode = ADD,AND,XOR,LDA (a binary operation)
3'b101 : if `LOG `outputs <= 9'b100000000;
else `outputs <= 9'b000000000; // operand fetch
3'b110 : instruction_operation; // instruction operation
3'b111 : store_result; // store result
endcase
state <= state + 1'b1;
end
task instruction_operation; //state 6
case (opcode)
`SKZ : if (zero) `outputs <= 9'b000001010;
else `outputs <= 9'b000000010;
`ADD, `AND, `XOR, `LDA : `outputs <= 9'b100000000;
`JMP : `outputs <= 9'b000010010;
default : `outputs <= 9'b000000010;
endcase
endtask
task store_result; //state 7
case (opcode)
`SKZ : if (zero) `outputs <= 9'b000001010;
else `outputs <= 9'b000000010;
`ADD, `AND, `XOR, `LDA : `outputs <= 9'b100100000;
`STO : `outputs <= 9'b010000010;
`JMP : `outputs <= 9'b000011010;
default: `outputs <= 9'b000000010;
endcase
endtask
endmodule
| 6.500738
|
module Seg7 (
input [3:0] num,
output [7:0] seg
);
reg [7:0] tseg;
always @(num) begin
case (num)
4'b0000: tseg = 8'b11111100; // 0
4'b0001: tseg = 8'b01100000; // 1
4'b0010: tseg = 8'b01011010; // 2
4'b0011: tseg = 8'b11110010; // 3
4'b0100: tseg = 8'b01100110; // 4
4'b0101: tseg = 8'b10110110; // 5
4'b0110: tseg = 8'b10111110; // 6
4'b0111: tseg = 8'b11100100; // 7
4'b1000: tseg = 8'b11111110; // 8
4'b1001: tseg = 8'b11110110; // 9
default: tseg = 8'b00000000; //
endcase
// seg = tseg;
end
assign seg = tseg;
endmodule
| 6.771186
|
module simple_function ();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a + b) + (c - d));
end
endfunction
endmodule
| 6.540619
|
module function_calling (
a,
b,
c,
d,
e,
f
);
input a, b, c, d, e;
output f;
wire f;
`include "myfunction.v"
assign f = (myfunction(a, b, c, d)) ? e : 0;
endmodule
| 7.144021
|
module items> có thể bao gồm：
1. initial
2. always
3. assign
4. module
/*****************************************/
/*****************************************/
//Example01：
module A(out1, out2, in1, in2);
output out1;
output [3:0] out2;
input in1;
input [2:0] in2;
endmodule
| 6.689213
|
module my_module (
Clk,
D,
Q
);
parameter width = 2, delay = 10;
input [width - 1 : 0] D;
input Clk;
output [width : 0] Q;
assign #delay Q = D;
endmodule
| 7.052055
|
module nandgate (
output s,
input p,
input q
);
assign s = ~(p & q);
endmodule
| 7.298658
|
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305
|
module fraserbc_simon (
io_in,
io_out
);
input wire [7:0] io_in;
output wire [7:0] io_out;
assign io_out[7:4] = 4'b0;
/* Instantiate main module */
simon simon0 (
.i_clk (io_in[0]),
.i_shift(io_in[1]),
.i_data (io_in[5:2]),
.o_data (io_out[3:0])
);
endmodule
| 7.617861
|
module lfsr_z0 (
i_clk,
i_rst,
o_data
);
input wire i_clk;
input wire i_rst;
output wire o_data;
reg [4:0] r_lfsr;
assign o_data = r_lfsr[0];
always @(posedge i_clk)
if (i_rst) r_lfsr <= 5'b00001;
else begin
r_lfsr[4] <= r_lfsr[3];
r_lfsr[3] <= r_lfsr[2];
r_lfsr[2] <= r_lfsr[4] ^ r_lfsr[1];
r_lfsr[1] <= r_lfsr[0];
r_lfsr[0] <= r_lfsr[4] ^ r_lfsr[0];
end
endmodule
| 7.510878
|
module simon (
i_clk,
i_shift,
i_data,
o_data
);
input wire i_clk;
input wire i_shift;
input wire [3:0] i_data;
output wire [3:0] o_data;
assign o_data = r_round[3:0];
/* z0 Sequence */
wire w_z0;
lfsr_z0 lfsr0 (
.i_clk (i_clk),
.i_rst (i_shift),
.o_data(w_z0)
);
/* Key Schedule */
reg [63:0] r_key;
wire [15:0] w_temp = r_key[31:16] ^ {r_key[50:48], r_key[63:51]}; // Right circular shift
always @(posedge i_clk) begin
if (i_shift) r_key <= {i_data, r_key[63:4]};
else begin
r_key[15:0] <= r_key[31:16];
r_key[31:16] <= r_key[47:32];
r_key[47:32] <= r_key[63:48];
r_key[63:48] <= (2**16 - 4) ^ {{15{1'b0}}, w_z0} ^ w_temp ^ r_key[15:0] ^ {w_temp[0],w_temp[15:1]};
end
end
/* Encrypt */
reg [31:0] r_round;
always @(posedge i_clk) begin
if (i_shift) r_round <= {r_key[3:0], r_round[31:4]};
else begin
r_round[15:0] <= r_round[31:16];
r_round[31:16] <= (({r_round[30:16],r_round[31]} & {r_round[23:16],r_round[31:24]})) ^ {r_round[29:16],r_round[31:30]} ^ r_key[15:0] ^ r_round[15:0];
end
end
endmodule
| 7.119927
|
module top_module (
output one
);
// Insert your code here
wire x;
assign one = 1'b1;
endmodule
| 7.203305
|
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 1;
b = 1;
end
// ------------------------- parte principal
initial begin
$display("Exercico 002 - Ailton Gomes - 440092");
$display("Test NOR gate");
$display("\n~(a | b) = s\n");
a = 0;
b = 0;
#1 $display("~(%b | %b) = %b", a, b, s);
a = 0;
b = 1;
#2 $display("~(%b | %b) = %b", a, b, s);
a = 1;
b = 0;
#3 $display("~(%b | %b) = %b", a, b, s);
a = 1;
b = 1;
#4 $display("~(%b | %b) = %b", a, b, s);
end
endmodule
| 6.695863
|
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305
|
module tomkeddie_top_tto #(
parameter CLOCK_RATE = 1000
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire hour_inc = io_in[6];
wire min_inc = io_in[7];
wire lcd_en;
wire lcd_rs;
wire [3:0] lcd_data;
assign io_out[0] = lcd_data[0];
assign io_out[1] = lcd_data[1];
assign io_out[2] = lcd_data[2];
assign io_out[3] = lcd_data[3];
assign io_out[4] = lcd_en;
assign io_out[5] = lcd_rs;
// instatiate lcd
lcd lcd (
.clk(clk),
.reset(reset),
.hour_inc(hour_inc),
.min_inc(min_inc),
.en(lcd_en),
.rs(lcd_rs),
.data(lcd_data)
);
endmodule
| 6.88019
|
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305
|
module xnorgate (
output s,
input p,
input q
);
assign s = (~p ^ q);
endmodule
| 6.74222
|
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores binarios
b = 0; // valores binarios
end
// ------------------------- parte principal
initial begin : main
$display("Exercico 003 - Ailton Gomes - 440092");
$display("Test xnor gate");
$display("\n ~(a ^ b) = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 0; // valores decimais
#1 a = 1;
b = 0;
#1 a = 0;
b = 1;
#1 a = 1;
b = 1;
end
endmodule
| 7.028584
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305
|
module nandgate (
output s,
input p,
input q
);
assign s = ((~p) | (~q));
endmodule
| 7.298658
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
// input, output은 따로 지정하지 않는 한 자동으로 wire 선언됨
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
output w,
x,
y,
z
);
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
| 7.203305
|
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 1;
b = 1;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 005 - Ailton Gomes - 440092");
$display("Test NOR gate");
$display("\n((~p) & (~q)) = s\n");
a = 0;
b = 0;
#1 $display("((~%b) & (~%b)) = %b", a, b, s);
a = 0;
b = 1;
#2 $display("((~%b) & (~%b)) = %b", a, b, s);
a = 1;
b = 0;
#3 $display("((~%b) & (~%b)) = %b", a, b, s);
a = 1;
b = 1;
#4 $display("((~%b) & (~%b)) = %b", a, b, s);
end
endmodule
| 6.695863
|
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305
|
module top_module (
input in,
output out
);
assign out = ~in;
endmodule
| 7.203305
|
module migcorre_pwm (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0]; // clock input 12.5KHz
wire reset = io_in[1]; // reset active high
wire increase_duty_in = io_in[2]; // increase duty cycle by 10%
wire decrease_duty_in = io_in[3]; // decrease duty cycle by 10%
wire disable_debouncer_in = io_in[4];
wire pwm_out; // 1.2kHz PWM output signal
wire increase_duty_sync;
wire decrease_duty_sync;
wire disable_debouncer_sync;
wire increase_duty_deb;
wire decrease_duty_deb;
wire increase_duty;
wire decrease_duty;
// Sinchronizers ------------------------/
synchronizer #(
.NUM_STAGES(2)
) synchronizer_increase_duty (
.clk(clk),
.async_in(increase_duty_in),
.sync_out(increase_duty_sync)
);
synchronizer #(
.NUM_STAGES(2)
) synchronizer_decrease_duty (
.clk(clk),
.async_in(decrease_duty_in),
.sync_out(decrease_duty_sync)
);
synchronizer #(
.NUM_STAGES(2)
) synchronizer_sisable_debouncer (
.clk(clk),
.async_in(disable_debouncer_in),
.sync_out(disable_debouncer_sync)
);
// Debuncers ------------------------/
debouncer #(
.N(8)
) increase_debuncer (
.clk(clk),
.reset(reset),
.signal_in(increase_duty_sync),
.signal_out(increase_duty_deb)
);
debouncer #(
.N(8)
) decrease_debuncer (
.clk(clk),
.reset(reset),
.signal_in(decrease_duty_sync),
.signal_out(decrease_duty_deb)
);
assign increase_duty = disable_debouncer_sync == 1 ? increase_duty_sync : increase_duty_deb;
assign decrease_duty = disable_debouncer_sync == 1 ? decrease_duty_sync : decrease_duty_deb;
// PWM ------------------------/
pwm #(
.INITIAL_DUTY(5)
) pwm_dc (
.clk(clk),
.reset(reset),
.increase_duty_in(increase_duty),
.decrease_duty_in(decrease_duty),
.pwm_out(pwm_out)
);
assign io_out[0] = pwm_out;
assign io_out[1] = ~pwm_out;
assign io_out[2] = increase_duty_sync;
assign io_out[3] = decrease_duty_sync;
endmodule
| 6.944077
|
module xorgate (
output s,
input p,
input q
);
assign s = ((~p) & q) | (p & (~q));
endmodule
| 7.421731
|
module testxorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores binarios
b = 0; // valores binarios
end
// ------------------------- parte principal
initial begin : main
$display("Exercicio 006 - Ailton Gomes - 440092");
$display("Test xor gate");
$display("\n ((~a) & b) | (a & (~b)) = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 0; // valores decimais
#1 a = 1;
b = 0;
#1 a = 0;
b = 1;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539
|
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305
|
module xnorgate (
output s,
input p,
input q
);
assign s = ((p & q) | ((~p) & (~q)));
endmodule
| 6.74222
|
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores binarios
b = 0; // valores binarios
end
// ------------------------- parte principal
initial begin : main
$display("Exercio 007 - Ailton Gomes - 440092");
$display("Test xnor gate");
$display("\n ((p & q)|((~p)&(~q))) = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 0; // valores decimais
#1 a = 1;
b = 0;
#1 a = 0;
b = 1;
#1 a = 1;
b = 1;
end
endmodule
| 7.028584
|
module alu_top (
input [7:0] io_in,
output [7:0] io_out
);
alu alu (
.A(io_in[7:6]),
.B(io_in[5:4]),
.ALU_Sel(io_in[3:0]),
.ALU_Out(io_out[6:0]),
.CarryOut(io_out[7])
);
endmodule
| 7.395278
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| 7.203305
|
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
c = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio008 - Ailton Gomes - 440092");
$display("Test AND gate");
$display("\na & b & c = s\n");
a = 0;
b = 0;
c = 0;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 1;
b = 0;
c = 0;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 0;
b = 1;
c = 0;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 1;
b = 1;
c = 0;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 0;
b = 0;
c = 1;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 1;
b = 0;
c = 1;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 0;
b = 1;
c = 1;
#1 $display("%b & %b & %b = %b", a, b, c, s);
a = 1;
b = 1;
c = 1;
#1 $display("%b & %b & %b = %b", a, b, c, s);
end
endmodule
| 6.553783
|
module for the McCoy microprocessor
*/
`default_nettype none
module aidan_McCoy(
input [7:0] io_in,
output [7:0] io_out);
// map i/o to proper labels
wire clk = io_in[0];
wire reset = io_in[1];
wire [5:0] instr = io_in[7:2];
// decode signals
wire bez;
wire ja;
//wire aluFun;
wire op1Sel;
wire op2Sel;
wire writeReg;
wire writex8;
wire [1:0] x8Sel;
// Other wires
wire [7:0] pc;
wire [7:0] pc1;
wire [7:0] nextPC;
wire pcSel;
wire [7:0] aluOut;
wire [7:0] x8;
wire [7:0] newx8;
wire [7:0] op1;
wire [7:0] op2;
wire [7:0] regOut;
wire [7:0] imm;
wire [7:0] notx8;
/* Misc. blocks */
decoder decoderBlock( .opcode(instr[2:0]), .bez(bez), .ja(ja), /*.aluFun(aluFun),*/ .op1(op1Sel), .op2(op2Sel),
.writeReg(writeReg), .writex8(writex8), .x8Sel(x8Sel));
iSign signBlock( .imm(instr[5:3]), .out(imm));
/* PC related blocks */
mux2 pcMux( .in0(aluOut), .in1(pc1), .sel(pcSel), .out(nextPC));
pc pcBlock( .clk(clk), .reset(reset), .nextPC(nextPC), .PC(pc));
add1 adder( .in(pc), .out(pc1));
branch branchBlock( .x8(x8), .bez(bez), .ja(ja), .reset(reset), .pcSel(pcSel));
/* ALU blocks */
mux2 op1Mux( .in0(regOut), .in1(x8), .sel(op1Sel), .out(op1));
mux2 op2Mux( .in0(regOut), .in1(pc), .sel(op2Sel), .out(op2));
alu aluBlock( .op1(op1), .op2(op2), /*.aluFun(aluFun),*/ .aluOut(aluOut));
/* x8 and other register blocks */
register regBlock( .clk(clk), .reset(reset), .regAddr(instr[5:3]), .x8(x8), .writeReg(writeReg),
.out(regOut));
x8 x8Block( .clk(clk), .writex8(writex8), .newx8(newx8), .x8(x8));
notx8 nx8( .x8(x8), .out(notx8));
mux4 x8Mux( .in0(regOut), .in1(imm), .in2(aluOut), .in3(notx8), .sel(x8Sel), .out(newx8));
assign io_out = clk ? pc : x8;
endmodule
| 7.59402
|
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a ~^ b;
endmodule
| 7.203305
|
module and2gate (
output t,
input a,
input b,
input c
);
wirel x;
andgate AND1 (
x,
a,
b
);
andgate AND2 (
t,
x,
d
);
endmodule
| 8.613407
|
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire u, s, t; // definir conexao (fio)
// ------------------------- instancia
and2gate AND3 (
u,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
c = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 009 - Ailton Gomes - 440092");
$display("Test AND gate");
$display("\n(a & b & c)= s\n");
#1 $monitor("(%b & %b & %b) = %b", a, b, c, u);
#1 a = 0;
b = 0;
c = 0;
#1 a = 0;
b = 0;
c = 1;
#1 a = 0;
b = 1;
c = 0;
#1 a = 0;
b = 1;
c = 1;
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 1;
#1 a = 1;
b = 1;
c = 0;
#1 a = 1;
b = 1;
c = 1;
end
endmodule
| 6.553783
|
module azdle_binary_clock (
input [7:0] io_in,
output [7:0] io_out
);
wire rst;
wire clk;
wire pps; // Pulse per second input
wire [4:0] hours_init; // value for hours to load when coming out of reset
wire [7:0] opins;
assign clk = io_in[0];
assign rst = io_in[1];
assign pps = io_in[2];
assign hours_init = io_in[7:3];
assign io_out = opins;
wire state;
wire d_roll; // rolls once per day
wire [4:0] hours;
wire h_roll; // rolls once per hour
wire [5:0] minutes;
wire m_roll; // rolls once per minute
wire [5:0] seconds;
wire s_roll; // rolls once per second
wire [6:0] centiseconds;
wire [11:0] pixels;
wire [6:0] disp_pins;
clock c (
.rst,
.clk,
.pps,
.hours_init,
.d_roll,
.h_roll,
.m_roll,
.s_roll,
.hours,
.minutes,
.seconds,
.centiseconds
);
display disp (
.rst,
.clk,
.pins(disp_pins),
.pixels
);
assign pixels = {hours, minutes, seconds[0]};
assign opins = rst ? 0 : {1'b0, disp_pins};
endmodule
| 7.186957
|
module rotor #(
parameter bits = 3,
parameter pattern = 6
) (
input rst,
input clk,
output reg [bits-1:0] val
);
always @(posedge clk)
if (rst) val <= pattern;
else val <= {val[bits-2:0], val[bits-1]};
endmodule
| 7.098426
|
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire and_1, and_2;
assign and_1 = a & b;
assign and_2 = c & d;
assign out = and_1 | and_2;
assign out_n = !out;
endmodule
| 7.203305
|
module top_module (
input wire a,
input wire b,
input wire c,
input wire d,
output wire out,
output wire out_n
);
wire and_ab_1;
wire and_cd_1;
wire or_2;
assign and_ab_1 = a & b;
assign and_cd_1 = c & d;
assign or_2 = and_ab_1 | and_cd_1;
assign out = or_2;
assign out_n = ~or_2;
endmodule
| 7.203305
|
module Circuit_1 (
A,
B,
C,
F1,
F2
);
output F1, F2;
input A, B, C;
and G1 (T2, A, B, C);
or G2 (T1, A, B, C);
and G3 (T4, A, B);
and G4 (T5, A, C);
and G5 (T6, B, C);
or G6 (F2, T4, T5, T6);
not G7 (T7, F2);
and G8 (T3, T1, T7);
or G9 (F1, T2, T3);
endmodule
| 7.03116
|
module top_module (
output one
);
// Insert your code here
assign one = 1; //assign allows to drive an output continuously with a value
endmodule
| 7.203305
|
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305
|
module top_module (
output zero
);
assign zero = 0;
endmodule
| 7.203305
|
module or3gate (
output s,
input p,
input q,
input r
);
wire x;
orgate OR0 (
x,
p,
q
);
orgate OR1 (
s,
r,
x
);
endmodule
| 7.416224
|
module testor3gate;
// ------------------------- dados locais
reg a, b, c; // definir registrador
wire s; // definir conexao (fio)
// ------------------------- instancia
or3gate OR1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0; // valores binarios
b = 0; // valores binarios
end
// ------------------------- parte principal
initial begin : main
$display("Exercicio 010 - Ailton Gomes - 440092");
$display("Test xor gate");
$display("\n (a | b) = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 0; // valores decimais
#1 a = 1;
b = 0;
#1 a = 0;
b = 1;
#1 a = 1;
b = 1;
end
endmodule
| 7.48966
|
module nand2 (
output s,
input a,
input b
);
assign s = (~(a & b));
endmodule
| 8.000232
|
module nor2 (
output s,
input a,
input b
);
assign s = (~(a | b));
endmodule
| 7.808103
|
module xnor2 (
output s,
input a,
input b
);
assign s = (~(a ^ b));
endmodule
| 7.055481
|
module nand2 (
output s,
input a,
input b
);
assign s = ((~a) | (~b));
endmodule
| 8.000232
|
module nor2 (
output s,
input a,
input b
);
assign s = ((~a) & (~b));
endmodule
| 7.808103
|
module xor2 (
output s,
input a,
input b
);
assign s = ((~a) & b) | (a & (~b));
endmodule
| 9.200725
|
module xnor2 (
output s,
input a,
input b
);
assign s = (a & b) | ((~a) & (~b));
endmodule
| 7.055481
|
module and3 (
output s,
input a,
input b,
input c
);
assign s = a & b & c;
endmodule
| 7.858068
|
module and3 (
output s,
input a,
input b,
input c
);
and and1 (w1, a, b);
and and2 (s, w1, c);
endmodule
| 7.858068
|
module detector (
input in,
input clk,
output out
);
reg out;
reg [1:0] state;
reg [1:0] nextstate;
//initializing state
initial begin
state <= 0;
end
//always block for state alloc
always @(posedge clk) begin
state <= nextstate;
end
//always block for next state
always @(in or state) begin
case (state)
0: nextstate <= (in == 0) ? 1 : 0;
1: nextstate <= (in == 1) ? 2 : 1;
2: nextstate <= (in == 0) ? 3 : 0;
3: nextstate <= (in == 0) ? 1 : 2;
endcase
end
//alwyas block for output logic
always @(state) begin
case (state)
0: out <= 0;
1: out <= 0;
2: out <= 0;
3: out <= 1;
default: out <= 0;
endcase
end
endmodule
| 6.593279
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire p1_and1, p1_and2, p2_and1, p2_and2;
assign p1_and1 = p1a & p1b & p1c;
assign p1_and2 = p1d & p1e & p1f;
assign p2_and1 = p2a & p2b;
assign p2_and2 = p2c & p2d;
assign p1y = p1_and1 | p1_and2;
assign p2y = p2_and1 | p2_and2;
endmodule
| 7.203305
|
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule
| 7.203305
|
module detector_tb;
/* input to the detector */
reg CLK;
reg in;
/* output from the detector */
wire out;
/* internal counter for test */
integer i;
integer Passed;
// Connect the detector to detector_tb
// Please follow name specified here.
detector UUT (
.clk(CLK),
.in (in),
.out(out)
);
/* Clock generator */
always #(`CLOCK_PERIOD / 2) CLK = ~CLK;
reg [0 : `PATTERN_LEN - 1] pattern;
reg [0 : `PATTERN_LEN - 1] ans;
initial begin
CLK = 0;
in = 0;
/* if you change the input stream, change the below */
pattern = `PATTERN_LEN'b00001101111101000010110010110011110000101101010111011011100000101111101011011011101010100001010001001100001110010000110011010010;
ans = `PATTERN_LEN'b00000000000000100001000001000000000000010000101000000000000000010000000100000000000101010000101000100000000000001000000000001001;
/* Checking # of passes */
Passed = 0;
#(`CLOCK_PERIOD);
for (i = 0; i < `PATTERN_LEN; i = i + 1) begin
in = pattern[i];
#(`CLOCK_PERIOD);
if (out == ans[i]) Passed = Passed + 1;
end
$display("Passed = %0d, Failed = %0d", Passed, `PATTERN_LEN - Passed);
$finish;
end
endmodule
| 7.485789
|
module or3 (
output s,
input a,
input b,
input c
);
or or1 (w1, a, b);
or or2 (s, w1, c);
endmodule
| 8.195932
|
module jar_sram_top #(
parameter AW = 4, // address width
parameter DW = 8, // data width
parameter DEPTH = 16 // number of bytes
) (
input [DW-1:0] io_in,
output [DW-1:0] io_out
);
// Shared address and data input.
// When writing, low data bits first, then high bits, then address
wire clk = io_in[0]; // Clock
wire we = io_in[1]; // Write Enable
wire oe = io_in[2]; // Output Enable
wire commit = io_in[3]; // Commit to memory
wire [AW-1:0] addr_data = io_in[DW-1:DW-AW];
reg [DW-1:0] data_tmp;
reg [DW-1:0] mem [DEPTH];
reg [AW-1:0] stream_index;
wire stream = we & oe;
wire reset = stream & commit;
always @(posedge clk) begin
if (reset) begin
stream_index <= addr_data;
end else if (stream) begin
data_tmp <= mem[stream_index];
stream_index <= stream_index + 1;
end else if (we) begin
data_tmp <= {addr_data, data_tmp[DW-1:AW]};
end else if (oe) begin
data_tmp <= mem[addr_data];
end else if (commit) begin
mem[addr_data] <= data_tmp;
end
end
assign io_out = (oe) ? data_tmp : 8'b0000_0000;
endmodule
| 7.064554
|
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o0 = vec[0];
assign o1 = vec[1];
assign o2 = vec[2];
endmodule
| 7.203305
|
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
| 7.203305
|
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
| 7.203305
|
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
endmodule
| 7.203305
|
module top_module (
input [31:0] in,
output [31:0] out
); //
// assign out[31:24] = ...;
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| 7.203305
|
module top_module (
input [31:0] in,
output [31:0] out
); //
// assign out[31:24] = ...;
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b, ~a};
endmodule
| 7.203305
|
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[5:3] = ~b;
assign out_not[2:0] = ~a;
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305
|
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| 7.203305
|
module tiny_fft (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire wrEn = io_in[2];
wire [3:0] data_in = io_in[7:4];
reg [1:0] wrIdx;
reg [2:0] rdIdx;
reg signed [3:0] input_reg[0:3];
assign io_out[0] = (rdIdx == 0) ? 1'b1 : 1'b0;
// Signal high when output value is real
assign io_out[1] = ~rdIdx[0];
always @(posedge clk) begin
if (reset) begin
wrIdx <= 0;
end else if (wrEn) begin
input_reg[wrIdx] <= data_in;
wrIdx <= wrIdx + 1;
end
end
wire [5:0] stage0_0 = input_reg[0] + input_reg[2];
wire [5:0] stage0_1 = input_reg[0] + ((~input_reg[2]) + 1);
wire [5:0] stage0_2 = input_reg[1] + input_reg[3];
wire [5:0] stage0_3 = input_reg[1] + ((~input_reg[3]) + 1);
wire [5:0] stage1[0:7];
// Freq bin 0 real + complex
assign stage1[0] = stage0_0 + stage0_2;
assign stage1[1] = 0;
// Freq bin 1 real + complex
assign stage1[2] = stage0_1;
assign stage1[3] = ((~stage0_3) + 1);
// Freq bin 2 real + complex
assign stage1[4] = ((~stage0_2) + 1) + stage0_0;
assign stage1[5] = 0;
// Freq bin 3 real + complex
assign stage1[6] = stage0_1;
assign stage1[7] = stage0_3;
assign io_out[7:2] = stage1[rdIdx];
always @(posedge clk) begin
if (reset) begin
rdIdx <= 0;
end else begin
rdIdx <= rdIdx + 1;
end
end
endmodule
| 7.212682
|
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305
|
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
// assign { ... } = { ... };
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305
|
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305
|
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}}, in};
endmodule
| 7.203305
|
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// assign out = { replicate-sign-bit , the-input };
assign out = {{24{in[7]}}, in};
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out = ~{{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^ {5{a, b, c, d, e}};
endmodule
| 7.203305
|
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
wire [24:0] A;
wire [24:0] B;
assign A = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
assign B = {5{a, b, c, d, e}};
assign out = A ~^ B;
endmodule
| 7.203305
|
module top_module (
input clk,
input reset,
output [9:0] q
);
reg [9:0] o_q;
assign q = o_q;
always @(posedge clk) begin
if (reset) begin
o_q <= 10'b0;
end else begin
if (o_q == 999) begin
o_q <= 10'b0;
end else begin
o_q <= o_q + 1;
end
end
end
endmodule
| 7.203305
|
module my_fsm1always (
clk,
reset,
inA,
inB,
OutA,
OutB
);
input clk, reset, inA, inB;
output OutA, OutB;
reg OutA = 0, OutB = 0;
reg [1:0] estado_actual = 0; // No empleo estado anterior
parameter E0 = 0, E1 = 1, E2 = 2, E3 = 3; // 4 estados posibles
//********************************* Parte 1 ****************************************************************
//Parte combinacional formada por procedimiento "always @( entradas y estado_actual )" **********************
// En un nico always de tipo combinacional, aadimos "las salidas" y el "clculo del siguiente estado" ******
//************************************************************************************************************
always @(posedge clk or posedge reset)
if (reset) begin
estado_actual <= E0; //Reset
OutA <= 0;
OutB <= 0;
end else begin
//Valores por defecto *************************************************************************
estado_actual <= 'bx; // asigno valores por defecto, se puede aadir aqu o como un default
OutA <= 0;
OutB <= 0;
//********************************************************************************************
case (estado_actual)
E0: begin
// aqu aadimos las salidas tambin en un nico always, en esta lnea
// no se aade porque la salida no cambia del valor por defecto inicial
case ({
inA, inB
}) // clculo del siguiente estado
0: estado_actual <= E0;
1: estado_actual <= E3;
2: estado_actual <= E1;
default: estado_actual <= E0;
endcase
end
E1: begin
OutB <= 1; //aado el valor de la salida que cambia de su valor por defecto
case ({
inA, inB
})
0: estado_actual <= E1;
1: estado_actual <= E2;
2: estado_actual <= E0;
default: estado_actual <= E1;
endcase
end
E2: begin
OutA <= 1; //aado el valor de la salida que cambia de su valor por defecto
case ({
inA, inB
})
0: estado_actual <= E2;
1: estado_actual <= E1;
2: estado_actual <= E3;
default: estado_actual <= E2;
endcase
end
E3: begin
{OutA, OutB} <= 3; //aado el valor de la salida que cambia de su valor por defecto
case ({
inA, inB
})
0: estado_actual <= E3;
1: estado_actual <= E0;
2: estado_actual <= E2;
default: estado_actual <= E3;
endcase
end
//default:estado_actual<='bx; // Esto nos previene de errores, ya que en un proceso de simulacin,
// si se nos ha olvidado codificar alguno de los estados, cuando pasemos por el estado no codificado
// nos aperecer que el estado siguiente ser XX y sabremos donde no hemos codificado el estado siguiente
endcase
end
endmodule
| 6.912463
|
module, the output port `b` is not driven; it isn't connected to any other wire.
// In general, all output ports of all modules should always be driven.
//
// In Verilog, one can connect two wires with the keyword `assign`.
// The following module implements a buffer (i.e. a circuit that copies its input to its output).
//
module buffer(
in,
out
);
input in;
output out;
assign out = in; // `in` drives `out`
endmodule
| 7.714843
|
module my_moore1 (
clk,
reset,
inA,
inB,
OutA,
OutB
);
input clk, reset, inA, inB;
output OutA, OutB;
reg OutA = 0, OutB = 0;
reg [1:0] estado_actual = 0, estado_siguiente = 0;
parameter E0 = 0, E1 = 1, E2 = 2, E3 = 3; // 4 estados posibles
//********************************* Parte 1 ****************************************************************
//Parte combinacional formada por procedimiento "always @( entradas y estado_actual )" **********************
//************************************************************************************************************
always @(inA or inB or estado_actual) begin
case (estado_actual)
E0: begin
case ({
inA, inB
})
0: estado_siguiente = E0;
1: estado_siguiente = E3;
2: estado_siguiente = E1;
default: estado_siguiente = E0;
endcase
end
E1: begin
case ({
inA, inB
})
0: estado_siguiente = E1;
1: estado_siguiente = E2;
2: estado_siguiente = E0;
default: estado_siguiente = E1;
endcase
end
E2: begin
case ({
inA, inB
})
0: estado_siguiente = E2;
1: estado_siguiente = E1;
2: estado_siguiente = E3;
default: estado_siguiente = E2;
endcase
end
E3: begin
case ({
inA, inB
})
0: estado_siguiente = E3;
1: estado_siguiente = E0;
2: estado_siguiente = E2;
default: estado_siguiente = E3;
endcase
end
default: estado_siguiente = E0;
endcase
end
// ************************** Parte 2 *****************************************************
// Parte secuencial, el estado_actual capturar el nuevo estado (estado_siguiente) ********
// ****************************************************************************************
always @(posedge clk or posedge reset) begin
if (reset) estado_actual <= E0;
else estado_actual <= estado_siguiente;
end
// ********************** Parte 3 (3a) ************************************************************
// Parte combinacional, se asigna un valor de salida en funcin del estado en el que nos encontramos
//**************************************************************************************************
always @(estado_actual) begin
case (estado_actual)
E0: {OutA, OutB} = 0;
E1: {OutA, OutB} = 1;
E2: {OutA, OutB} = 2;
E3: {OutA, OutB} = 3;
default: {OutA, OutB} = 0;
endcase
end
endmodule
| 7.179981
|
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
); //
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = in ? A : B;
B: next_state = in ? B : A;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if (areset) begin
state <= B;
end else begin
state <= next_state;
end
end
// Output logic
assign out = (state == B);
endmodule
| 7.203305
|
module sync_fifo_ver1 (
clk,
rst_n,
buf_in,
buf_out,
wr_en,
rd_en,
buf_empty,
buf_full,
fifo_cnt
);
input clk, rst_n;
input wr_en, rd_en;
input [7:0] buf_in;
output reg [7:0] buf_out;
output wire buf_empty, buf_full;
output reg [`buf_width-1:0] fifo_cnt;
reg [`buf_size-2:0] rd_ptr, wr_ptr;
reg [7:0] buf_mem[0:`buf_size-1];
//判断空满
assign buf_empty = (fifo_cnt == 0);
assign buf_full = (fifo_cnt == `buf_size);
always @(posedge clk or negedge rst_n)
if (!rst_n) fifo_cnt <= 0;
else if ((!buf_full && wr_en) && (!buf_empty && rd_en)) fifo_cnt <= fifo_cnt;
else if (!buf_full && wr_en) fifo_cnt <= fifo_cnt + 1'b1;
else if (!buf_empty && rd_en) fifo_cnt <= fifo_cnt - 1'b1;
else fifo_cnt <= fifo_cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) buf_out <= 0;
if (rd_en && !buf_empty) buf_out <= buf_mem[rd_ptr];
end
always @(posedge clk or negedge rst_n) if (wr_en && !buf_full) buf_mem[wr_ptr] <= buf_in;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
wr_ptr <= 0;
rd_ptr <= 0;
end else begin
if (!buf_full && wr_en) wr_ptr <= wr_ptr + 1'b1;
if (!buf_empty && rd_en) rd_ptr <= rd_ptr + 1'b1;
end
endmodule
| 6.509696
|
module sync_fifo_ver1_tb ();
reg clk, rst_n;
reg wr_en, rd_en;
reg [7:0] buf_in; // data input to be pushed to buffer
wire [7:0] buf_out; // port to output the data using pop.
wire buf_empty, buf_full; // buffer empty and full indication
wire [`BUF_WIDTH-1:0] fifo_cnt; // number of data pushed in to buffer
sync_fifo_ver1 dut (
clk,
rst_n,
buf_in,
buf_out,
wr_en,
rd_en,
buf_empty,
buf_full,
fifo_cnt
);
always #10 clk = ~clk;
reg [7:0] tempdata = 0;
initial begin
clk = 0;
rst_n = 0;
wr_en = 0;
rd_en = 0;
buf_in = 0;
#15;
rst_n = 1;
push(1);
fork
push(2);
pop(tempdata);
join //push and pop together
push(10);
push(20);
push(30);
push(40);
push(50);
push(60);
push(70);
push(80);
push(90);
push(100);
push(110);
push(120);
push(130);
pop(tempdata);
push(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
push(140);
pop(tempdata);
push(tempdata); //
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
push(5);
pop(tempdata);
end
task push(input [7:0] data);
if (buf_full) $display("---Cannot push %d: Buffer Full---", data);
else begin
$display("Push",, data);
buf_in = data;
wr_en = 1;
@(posedge clk);
#5 wr_en = 0;
end
endtask
task pop(output [7:0] data);
if (buf_empty) $display("---Cannot Pop: Buffer Empty---");
else begin
rd_en = 1;
@(posedge clk);
#3 rd_en = 0;
data = buf_out;
$display("------Poped:",, data);
end
endtask
endmodule
| 6.509696
|
module Circuit_2 (
Out_1,
Out_2,
Out_3,
A,
B,
C,
D
);
output Out_1, Out_2, Out_3;
input A, B, C, D;
assign Out_1 = (A || (!B)) && (!C) && (C || D);
assign Out_2 = ((!C) && D || (B && C && D) || (C && (!D))) && ((!A) || B);
assign Out_3 = (A && B || C) && D || (!B) && C;
endmodule
| 6.567869
|
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 0;
endmodule
| 7.203305
|
module top_module (
output zero
); // Module body starts after semicolon
assign zero = 1'b0;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
mod_a u_mod_a (
.in1(a),
.in2(b),
.out(out)
);
endmodule
| 7.203305
|
module top_module (
input a,
input b,
output out
);
mod_a instance1 (
.in1(a),
.in2(b),
.out(out)
);
endmodule
| 7.203305
|
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